1. Field of the Invention
The present invention relates to a semiconductor circuit designing apparatus and a semiconductor circuit designing method. More particularly, the present invention relates to a semiconductor circuit designing apparatus and a semiconductor circuit designing method, which are used in a silicon interface field of an ASIC development so as to further reduce the number of steps in a circuit design and a layout design.
2. Description of the Related Art
In a field of a semiconductor design, a division between a circuit design and a layout design is advanced as a circuit becomes large and complex, and the respective automations are advanced. In such division, an acceptance inspection is executed for examining whether or not a circuit information interfaced so as to minimize a backward motion of a step is reasonable. Inspection items for such an acceptance inspection are different depending on a circuit feature, such as a circuit configuration, a test simplifying method to be used and the like. So, the items of the acceptance inspection to be executed are determined depending on the circuit feature.
A layout designer carries out all necessary acceptance inspections for each model, on the basis of the circuit information prepared by the circuit designer. So, a number of steps are needed in order to execute the acceptance inspection and confirm the result. Or, there may be a case that an acceptance inspection on the layout designer side is omitted by inquiring the executed inspection items of the circuit designer. However, an answer (entry) miss on the circuit designer side, a misunderstanding or the like causes an erroneous result to be reported, which results in the backward motion of the step (iteration) in many cases.
A known drawing validation system disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 10-198708) includes a first memory for storing a data indicative of a drawing, a second memory for storing a data indicative of a predetermined condition and a judging unit for judging whether or not the drawing agrees with the predetermined condition. Such a drawing validation system can automatically validate whether or not an item specified on the basis of a know-how and an experience of the circuit designer is accurately reflected to thereby prepare a drawing of a layout of a printed circuit board, without any manual work. Thus, it is possible to prepare the drawing with high quality in a short time.
This drawing validation system relates to a determination of an inspection item and an inspection execution in a single drawing validation system to be used by the layout designer. Its applicable department is limited to the layout designer side. Thus, it does not disclose a method to be used for the circuit designer to avoid a problem.
Japanese Laid Open Patent Application (JP-A-Heisei, 10-79435) discloses the following semiconductor development information integrating apparatus. In a semiconductor information managing apparatus, the electronic data based on a photo-mask specification prepared in a semiconductor design and the electronic data in respective manufacturing processes prepared in a semiconductor manufacturing process are stored and managed in a same data or a plurality of databases as an integrated semiconductor information. Thus, the information with regard to a CAD apparatus, a semiconductor manufacturing electronic terminal and a semiconductor manufacturing apparatus are shared.